Overview
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash memory organized as 65,536/131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-volt-age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC package.
The AT25F512/1024 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
